A FPGA is a gate array. The information concerning input terminals, output terminals and internal logic function circuits of the FPGA can be managed as configuration data, and the logic circuit of the FPGA can be changed in the field. Therefore, FPGA has now been widely used in data processing systems and communication systems as a hardware featuring a high degree of general applicability.
The configuration data is stored in an external memory separate from the FPGAs, read out as required from the external memory and written into the FPGAs. Upon determining the configuration of the FPGAs, a hardware function can be realized based on the configuration data.
When a plurality of FPGAs are to be configured, a dedicated configuration circuit is provided for each of the FPGAs results in a problem concerning the cost and mounting areas on the circuit board.
According to the computer system described in Japanese Laid-open Patent Publication No. 2005-259053, as illustrated in FIG. 1, a data distribution function unit is provided to store the configuration data for a plurality of FPGAs in a flash ROM and to distribute the data to the plurality of FPGAs in an attempt to share the memory for storing the configuration data, and therefore decrease the number of parts.
The computer system 90 illustrated in FIG. 1 includes a configuration circuit which has an FROM (flash memory) 91 for storing the configuration data of FPGAs 91a to 94c, a CPU 92 and an FPGA data distribution function unit 93; and the FPGAs 94a to 94c which start working upon downloading the configuration data from the FPGA data distribution function unit 93.
FIG. 2 is a block diagram illustrating the constitution of the FPGA data distribution function unit 93. The FPGA data distribution function unit 93 includes an FROM access control unit 100, a sequence identification unit 101, first to third manufacturer identification units 102, 103 and 104, first to third FPGA interface units 105, 106 and 107, and a configuration completion detector unit 108. The FROM access control unit 100 reads out the configuration data stored in the FROM 91, discontinues the access to the FROM 91 when setting the configuration data has finished, and relays the access from the CPU 92 to the FROM 91.
The sequence identification unit 101 identifies the kind of sequence from the configuration data read out from the FROM access control unit 100, and outputs the configuration data to a path which is designated based on the kind of sequence that is identified.
The manufacturer identification units 102, 103 and 104 identify the manufacturers from the configuration data output to the paths, and output the identification of the manufacturers together with the configuration data.
Based on the identification of the manufacturers, the FPGA interface units 105, 106 and 107 convert the configuration data into the data of layouts specific to the manufacturers and output them.
The configuration completion detector unit 108 monitors the configuration statuses of the FPGAs 94a to 94c, and send them to the FROM access control unit 100.
Japanese Laid-open Patent Publication JP-11-144662 discloses an image processing apparatus in which a controller selects a configuration data out of a plurality of configuration data to start up the configuration.